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PMC.P4(3) MidnightBSD Library Functions Manual PMC.P4(3)

pmc.p4 — measurement events for Intel Pentium 4 and other Netburst architecture CPUs

Performance Counters Library (libpmc, -lpmc)

#include <pmc.h>

Intel P4 PMCs are present in Intel Pentium 4 and Xeon processors that use the Netburst CPU architecture.

These PMCs are documented in Volume 3: System Programming Guide, IA-32 Intel(R) Architecture Software Developer's Manual, Order Number 245472-012, Intel Corporation, 2003. Further information about using these PMCs may be found in IA-32 Intel(R) Architecture Optimization Guide, Order Number 248966-009, Intel Corporation, 2003. Some of these events are affected by processor errata described in Intel(R) Pentium(R) 4 Processor Specification Update, Document Number: 249199-059, Intel Corporation, April 2005.

Intel Pentium 4 PMCs are 40 bits wide. Each CPU contains 18 PMCs, divided into 4 groups with 4, 4, 4 and 6 PMCs respectively. On processors with hyperthreading support, PMC resources are shared between logical processors. These PMCs support the following capabilities:

PMC_CAP_CASCADE Yes
PMC_CAP_EDGE Yes
PMC_CAP_INTERRUPT Yes
PMC_CAP_INVERT Yes
PMC_CAP_READ Yes
PMC_CAP_PRECISE Unimplemented
PMC_CAP_SYSTEM Yes
PMC_CAP_TAGGING Yes
PMC_CAP_THRESHOLD Yes
PMC_CAP_USER Yes
PMC_CAP_WRITE Yes

Event specifiers for Intel P4 PMCs can have the following common qualifiers:

choice
(On P4 HTT CPUs) Filter event counting based on which logical processors are active. The allowed values of choice are:

Count when either logical processor is active.
Count when both logical processors are active.
Count only when neither logical processor is active.
Count only when one logical processor is active.

The default is “both”.

Configure the PMC to cascade onto its partner. See Cascading P4 PMCs below for more information.
Configure the counter to count false to true transitions of the threshold comparison output. This qualifier only takes effect if a threshold qualifier has also been specified.
Configure the counter to increment only when the event count seen is less than the threshold qualifier value specified.
qualifier
Many event specifiers for Intel P4 PMCs need to be additionally qualified using a mask qualifier. The allowed syntax for these qualifiers is event specific and is described along with the events.
Configure the PMC to count when the CPL of the processor is 0.
Select precise event based sampling. Precise sampling is supported by the hardware for a limited set of events.
value
Configure the PMC to tag the internal uop selected by the other fields in this event specifier with value value. This feature is used when cascading PMCs.
value
Configure the PMC to increment only when the event counts seen are greater than the specified threshold value value.
Configure the PMC to count when the CPL of the processor is 1, 2 or 3.

If neither of the “os” or “usr” qualifiers are specified, the default is to enable both.

On Intel Pentium 4 processors with HTT, events are divided into two classes:

TS Events
are those where hardware can differentiate between events generated on one logical processor from those generated on the other.
TI Events
are those where hardware cannot differentiate between events generated by multiple logical processors in a package.

Only TS events are allowed for use with process-mode PMCs on Pentium-4/HTT CPUs.

The event specifiers supported by Intel P4 PMCs are:

[,mask=flags]
(TI event) Count integer SIMD SSE2 instructions that operate on 128 bit SIMD operands. Qualifier flags can take the following value (which is also the default):

Count all uops operating on 128 bit SIMD integer operands in memory or XMM register.

If an instruction contains more than one 128 bit MMX uop, then each uop will be counted.

[,mask=flags]
(TI event) Count MMX instructions that operate on 64 bit SIMD operands. Qualifier flags can take the following value (which is also the default):

Count all uops operating on 64 bit SIMD integer operands in memory or in MMX registers.

If an instruction contains more than one 64 bit MMX uop, then each uop will be counted.

(TI event) Count back-to-back bus cycles. Further documentation for this event is unavailable.
(TI event) Count bus-not-ready conditions. Further documentation for this event is unavailable.
[,mask=qualifier]
(TS event) Count instruction fetch requests qualified by additional flags specified in qualifier. At this point only one flag is supported:

Count trace cache lookup misses.

The default qualifier is also “mask=tcmiss”.

[,mask=flags]
(TS event) Counts retired branches. Qualifier flags is a list of the following ‘+’ separated strings:

Count branches not-taken and predicted.
Count branches not-taken and mis-predicted.
Count branches taken and predicted.
Count branches taken and mis-predicted.

The default qualifier counts all four kinds of branches.

[,mask=qualifier]
(TS event) Count the number of entries (clipped at 15) currently active in the BSQ. Qualifier qualifier is a ‘+’ separated set of the following flags:

, req-type1
Forms a 2-bit number used to select the request type encoding:

reads excluding read invalidate
read invalidates
writes other than writebacks
writebacks

Bit “req-type1” is the MSB for this two bit number.

, req-len1
Forms a two-bit number that specifies the request length encoding:

0 chunks
1 chunk
8 chunks

Bit “req-len1” is the MSB for this two bit number.

Count requests that are input or output requests.
Count requests that lock the bus.
Count requests that lock the cache.
Count requests that is a bus 8-byte chunk that is split across an 8-byte boundary.
Count requests that are demand (not prefetches) if set. Count requests that are prefetches if not set.
Count requests that are ordered.
, mem-type1, mem-type2
Forms a 3-bit number that specifies a memory type encoding:

UC
USWC
WT
WP
WB

Bit “mem-type2” is the MSB of this 3-bit number.

The default qualifier has all the above bits set.

Edge triggering using the “edge” qualifier should not be used with this event when counting cycles.

[,mask=qualifier]
(TS event) Count allocations in the bus sequence unit according to the flags specified in qualifier, which is a ‘+’ separated set of the following flags:

, req-type1
Forms a 2-bit number used to select the request type encoding:

reads excluding read invalidate
read invalidates
writes other than writebacks
writebacks

Bit “req-type1” is the MSB for this two bit number.

, req-len1
Forms a two-bit number that specifies the request length encoding:

0 chunks
1 chunk
8 chunks

Bit “req-len1” is the MSB for this two bit number.

Count requests that are input or output requests.
Count requests that lock the bus.
Count requests that lock the cache.
Count requests that is a bus 8-byte chunk that is split across an 8-byte boundary.
Count requests that are demand (not prefetches) if set. Count requests that are prefetches if not set.
Count requests that are ordered.
, mem-type1, mem-type2
Forms a 3-bit number that specifies a memory type encoding:

UC
USWC
WT
WP
WB

Bit “mem-type2” is the MSB of this 3-bit number.

The default qualifier has all the above bits set.

This event is usually used along with the “edge” qualifier to avoid multiple counting.

[,mask=qualifier]
(TS event) Count cache references as seen by the bus unit (2nd or 3rd level cache references). Qualifier qualifier is a ‘+’ separated list of the following keywords:

Count 2nd level cache hits in the shared state.
Count 2nd level cache hits in the exclusive state.
Count 2nd level cache hits in the modified state.
Count 3rd level cache hits in the shared state.
Count 3rd level cache hits in the exclusive state.
Count 3rd level cache hits in the modified state.
Count 2nd level cache misses.
Count 3rd level cache misses.
Count write-back lookups from the data access cache that miss the 2nd level cache.

The default is to count all the above events.

[,mask=flags]
(TS event) Count the retirement of tagged uops selected through the execution tagging mechanism. Qualifier flags can contain the following strings separated by ‘+’ characters:

, nbogus1, nbogus2, nbogus3
The marked uops are not bogus.
, bogus1, bogus2, bogus3
The marked uops are bogus.

This event requires additional (upstream) events to be allocated to perform the desired uop tagging. The default is to set all the above flags. This event can be used for precise event based sampling.

[,mask=flags]
(TS event) Count the retirement of tagged uops selected through the front-end tagging mechanism. Qualifier flags can contain the following strings separated by ‘+’ characters:

The marked uops are not bogus.
The marked uops are bogus.

This event requires additional (upstream) events to be allocated to perform the desired uop tagging. The default is to select both kinds of events. This event can be used for precise event based sampling.

[,mask=flags]
(TI event) Count each DBSY or DRDY event selected by qualifier flags. Qualifier flags is a ‘+’ separated set of the following flags:

Count when this processor is driving data onto the bus.
Count when this processor is reading data from the bus.
Count when data is on the bus but not being sampled by this processor.
Count when this processor reserves the bus for use in the next cycle in order to drive data.
Count when some agent reserves the bus for use in the next bus cycle to drive data that this processor will sample.
Count when some agent reserves the bus for use in the next bus cycle to drive data that this processor will not sample.

Flags “drdy-own” and “drdy-other” are mutually exclusive. Flags “dbsy-own” and “dbsy-other” are mutually exclusive. The default value for qualifier is “drdy-drv+drdy-own+dbsy-drv+dbsy-own”.

[,mask=flags]
(TS event) Count cycles during which the processor is not stopped. Qualifier flags can take the following value (which is also the default):

Count cycles when the processor is active.
[,mask=flags]
(TS event) Count instructions retired during a clock cycle. Qualifier flags comprises of the following strings separated by ‘+’ characters:

Count non-bogus instructions that are not tagged.
Count non-bogus instructions that are tagged.
Count bogus instructions that are not tagged.
Count bogus instructions that are tagged.

The default qualifier counts all the above kinds of instructions.

[,mask=qualifier] [,busreqtype=req-type]
(TS event) Count the number of entries (clipped at 15) in the IOQ that are active. The event masks are specified by qualifier qualifier and req-type.

Qualifier qualifier is a ‘+’ separated set of the following flags:

Count read entries.
Count write entries.
Count entries accessing un-cacheable memory.
Count entries accessing write-combining memory.
Count entries accessing write-through memory.
Count entries accessing write-protected memory
Count entries accessing write-back memory.
Count store requests driven by the processor (i.e., not by other processors or by DMA).
Count store requests driven by other processors or by DMA.
Include hardware and software prefetch requests in the count.

The default value for qualifier is to enable all the above flags.

The req-type qualifier is a 5-bit number can be additionally used to select a specific bus request type. The default is 0.

The “edge” qualifier should not be used when counting cycles with this event. The exact behavior of this event depends on the processor revision.

[,mask=qualifier] [,busreqtype=req-type]
(TS event) Count various types of transactions on the bus matching the flags set in qualifier and req-type.

Qualifier qualifier is a ‘+’ separated set of the following flags:

Count read entries.
Count write entries.
Count entries accessing un-cacheable memory.
Count entries accessing write-combining memory.
Count entries accessing write-through memory.
Count entries accessing write-protected memory
Count entries accessing write-back memory.
Count store requests driven by the processor (i.e., not by other processors or by DMA).
Count store requests driven by other processors or by DMA.
Include hardware and software prefetch requests in the count.

The default value for qualifier is to enable all the above flags.

The req-type qualifier is a 5-bit number can be additionally used to select a specific bus request type. The default is 0.

The “edge” qualifier is normally used with this event to prevent multiple counting. The exact behavior of this event depends on the processor revision.

[mask=qualifier]
(TS event) Count translations using the instruction translation look-aside buffer. The qualifier argument is a list of the following strings separated by ‘+’ characters.

Count ITLB hits.
Count ITLB misses.
Count un-cacheable ITLB hits.

If no qualifier is specified the default is to count all the three kinds of ITLB translations.

[,mask=qualifier]
(TS event) Count replayed events at the load port. Qualifier qualifier can take on one value:

Count split loads.

The default value for qualifier is “split-ld”.

[,mask=flags]
(TS event) Count mispredicted IA-32 branch instructions. Qualifier flags can take the following value (which is also the default):

Count non-bogus retired branch instructions.
[,mask=flags]
(TS event) Count the number of pipeline clears seen by the processor. Qualifier flags is a list of the following strings separated by ‘+’ characters:

Count for a portion of the many cycles when the machine is being cleared for any reason.
Count machine clears due to memory ordering issues.
Count machine clears due to self-modifying code.

Use qualifier “edge” to get a count of occurrences of machine clears. The default qualifier is “clear”.

[,mask=event-list]
(TS event) Count the canceling of various kinds of requests in the data cache address control unit of the CPU. The qualifier event-list is a list of the following strings separated by ‘+’ characters:

Requests cancelled because no store request buffer was available.
Requests that conflict due to 64K aliasing.

If event-list is not specified, then the default is to count both kinds of events.

[,mask=event-list]
(TS event) Count the completion of load split, store split, un-cacheable split and un-cacheable load operations selected by qualifier event-list. The qualifier event-list is a ‘+’ separated list of the following flags:

Count load splits completed, excluding loads from un-cacheable or write-combining areas.
Count any split stores completed.

The default is to count both kinds of operations.

[,mask=qualifier]
(TS event) Count load replays triggered by the memory order buffer. Qualifier qualifier can be a ‘+’ separated list of the following flags:

Count replays because of unknown store addresses.
Count replays because of unknown store data.
Count replays because of partially overlapped data accesses between load and store operations.
Count replays because of mismatches in the lower 4 bits of load and store operations.

The default qualifier is no-sta+no-std+partial-data+unalgn-addr.

[,mask=flags]
(TI event) Count packed double-precision uops. Qualifier flags can take the following value (which is also the default):

Count all uops operating on packed double-precision operands.
[,mask=flags]
(TI event) Count packed single-precision uops. Qualifier flags can take the following value (which is also the default):

Count all uops operating on packed single-precision operands.
[,mask=qualifier]
(TI event) Count page walks performed by the page miss handler. Qualifier qualifier can be a ‘+’ separated list of the following keywords:

Count page walks for data TLB misses.
Count page walks for instruction TLB misses.

The default value for qualifier is “dtmiss+itmiss”.

[,mask=flags]
(TS event) Count the retirement of tagged uops selected through the replay tagging mechanism. Qualifier flags contains a ‘+’ separated set of the following strings:

The marked uops are not bogus.
The marked uops are bogus.

This event requires additional (upstream) events to be allocated to perform the desired uop tagging. The default qualifier counts both kinds of uops. This event can be used for precise event based sampling.

[,mask=flags]
(TS event) Count the occurrence or latency of stalls in the allocator. Qualifier flags can take the following value (which is also the default):

A stall due to the lack of store buffers.
(TI event) Count different types of responses. Further documentation on this event is not available.
[,mask=flags]
(TS event) Count branches retired. Qualifier flags contains a ‘+’ separated list of strings:

Count conditional jumps.
Count direct and indirect call branches.
Count return branches.
Count returns, indirect calls or indirect jumps.

The default qualifier counts all the above branch types.

[,mask=flags]
(TS event) Count mispredicted branches retired. Qualifier flags contains a ‘+’ separated list of strings:

Count conditional jumps.
Count indirect call branches.
Count return branches.
Count returns, indirect calls or indirect jumps.

The default qualifier counts all the above branch types.

[,mask=flags]
(TI event) Count the number of scalar double-precision uops. Qualifier flags can take the following value (which is also the default):

Count the number of scalar double-precision uops.
[,mask=flags]
(TI event) Count the number of scalar single-precision uops. Qualifier flags can take the following value (which is also the default):

Count all uops operating on scalar single-precision operands.
(TI event) Count snoop traffic. Further documentation on this event is not available.
[,mask=flags]
(TI event) Count the number of times an assist is required to handle problems with the operands for SSE and SSE2 operations. Qualifier flags can take the following value (which is also the default):

Count assists for all SSE and SSE2 uops.
[,mask=qualifier]
(TS event) Count events replayed at the store port. Qualifier qualifier can take on one value:

Count split stores.

The default value for qualifier is “split-st”.

[,mask=qualifier]
(TI event) Count the duration in cycles of operating modes of the trace cache and decode engine. The desired operating mode is selected by qualifier, which is a list of the following strings separated by ‘+’ characters:

Both logical processors are in deliver mode.
Logical processor 0 is in deliver mode while logical processor 1 is in build mode.
Logical processor 0 is in deliver mode while logical processor 1 is halted, or in machine clear, or transitioning to a long microcode flow.
Logical processor 0 is in build mode while logical processor 1 is in deliver mode.
Both logical processors are in build mode.
Logical processor 0 is in build mode while logical processor 1 is halted, or in machine clear or transitioning to a long microcode flow.
Logical processor 0 is halted, or in machine clear or transitioning to a long microcode flow while logical processor 1 is in deliver mode.
Logical processor 0 is halted, or in machine clear or transitioning to a long microcode flow while logical processor 1 is in build mode.

If there is only one logical processor in the processor package then the qualifier for logical processor 1 is ignored. If no qualifier is specified, the default qualifier is “DD+DB+DI+BD+BB+BI+ID+IB”.

[,mask=flags]
(TI event) Count the number of times uop delivery changed from the trace cache to MS ROM. Qualifier flags can take the following value (which is also the default):

Count TC to MS transfers.
[,mask=flags]
(TS event) Count the number of valid uops written to the uop queue. Qualifier flags is a list of the following strings, separated by ‘+’ characters:

Count uops being written from the trace cache in build mode.
Count uops being written from the trace cache in deliver mode.
Count uops being written from microcode ROM.

The default qualifier counts all the above kinds of uops.

[,mask=flags]
(TS event) This event is used in conjunction with the front-end at-retirement mechanism to tag load and store uops. Qualifier flags comprises the following strings separated by ‘+’ characters:

Mark uops that are load operations.
Mark uops that are store operations.

The default qualifier counts both kinds of uops.

[,mask=flags]
(TS event) Count uops retired during a clock cycle. Qualifier flags comprises the following strings separated by ‘+’ characters:

Count marked uops that are not bogus.
Count marked uops that are bogus.

The default qualifier counts both kinds of uops.

[,mask=flags]
(TI event) Count write-combining buffer operations. Qualifier flags contains the following strings separated by ‘+’ characters:

WC buffer evictions due to any cause.
WC buffer evictions due to no WC buffer being available.

The default qualifier counts both kinds of evictions.

[,mask=flags]
(TS event) Count the retirement of x87 instructions that required special handling. Qualifier flags contains the following strings separated by ‘+’ characters:

Count instructions that saw an FP stack underflow.
Count instructions that saw an FP stack overflow.
Count instructions that saw an x87 output overflow.
Count instructions that saw an x87 output underflow.
Count instructions that needed an x87 input assist.

The default qualifier counts all the above types of instruction retirements.

[,mask=flags]
(TI event) Count x87 floating-point uops. Qualifier flags can take the following value (which is also the default):

Count all x87 floating-point uops.

If an instruction contains more than one x87 floating-point uops, then all x87 floating-point uops will be counted. This event does not count x87 floating-point data movement operations.

[,mask=flags]
(TI event) Count each x87 FPU, MMX, SSE, or SSE2 uops that load data or store data or perform register-to-register moves. This event does not count integer move uops. Qualifier flags may contain the following keywords separated by ‘+’ characters:

Count all x87 and SIMD store and move uops.
Count all x87 and SIMD load uops.

The default is to count all uops. (Errata) This event may be affected by processor errata N43.

PMC cascading support is currently poorly implemented. While individual event counters may be allocated with a “cascade” qualifier, the current API does not offer the ability to name and allocate all the resources needed for a cascaded event counter pair in a single operation.

Support for precise event based sampling is currently unimplemented.

The following table shows the mapping between the PMC-independent aliases supported by Performance Counters Library (libpmc, -lpmc) and the underlying hardware events used.

(unsupported)
(unsupported)

pmc(3), pmc.atom(3), pmc.core(3), pmc.core2(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3), pmc.p5(3), pmc.p6(3), pmc.soft(3), pmc.tsc(3), pmclog(3), hwpmc(4)

The pmc library first appeared in FreeBSD 6.0.

The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org>.

October 4, 2008 midnightbsd-3.1